As information processing systems such as personal computers have become more popular and have been used in various fields, improving processing performance. For improving the performance, an approach that a plurality of processors is incorporated in an information processing system has been proposed. For this structure, high speed data transfer between the plurality of processors is an important factor in ensuring high performance. Typical high speed connection systems include the ring connection system, the conventional bus system and the switch system, which are shown, respectively, in FIGS. 1A, 1B and 1C.
The bus system is most popular as the connection means between processors that achieves high speed data transfer. The bus system does not need external additional circuits for connection and is flexible for expansion, and needs fewer number of pins which are necessary for connectors and is inexpensive. Further, all processors can see the content of the bus, therefore this system is suitable for broadcast communication (snoop) of tightly-coupled inter-processor connection.
For the bus connection system shown in FIG. 1A, the communication capacity, which is an important determinant of the performance and number of processors to be connected, depends on the clock frequency. In the processor bus, the time difference for signal transmission to the nearest processor and to the farthest processor should be included in the same clock cycle, so the operating frequency is limited by the bus length. The design value of the clock, LSI, and skew of the transmission line influence directly on the operating frequency. Because of the possibility of all of the combinations of transmitters and receivers, suitable for skew correction cannot be achieved. Degradation of transmission performance due to both-way transmission of a signal from outgoing lines to processors and passage in outgoing lines, and also the limitation on the operating frequency due to the necessity of providing an adequate driving capability to all of the processors are the main limiting conditions. To compensate, the length of the bus can be shortened to improve the operation frequency, but this puts a limitation on the flexibility in design regarding the mounting of the processors of the microprocessor systems. The operating frequency is improved by transmitting clock and data together, but the frequent switching between processors in the processor bus causes long switching times. The number of processors to be connected is also limited electrically. Further, the delay for acquisition of transmission right on the bus causes another performance limitation. There is also the problem of high performance connection between processors in the case that switching of inter-processor transfer is frequent whereby consistent response is not obtained from the processors.
FIG. 1C shows a switch connection system for LSI processors. When a switch system is used for connecting processors, a signal is transferred one way, and the operating frequency is improved because of the one-to-one communication. The total communication capacity is not limited theoretically, and the number of connections is not limited. On the other hand, the switch is an external component and connection between the processors is star-like. As a result, the total length of wiring is significant and the wiring around the switch becomes crowded. Further, the broadcast communication makes the control complex and the delay time due to passage through the switch also limits the performance.
A ring connection system is shown in FIG. 1B. The ring is also used for connection between processors. In the ring connection system, a signal is transferred in one way with one-to-one correspondence, therefore the communication capacity can be made larger than that of the bus system. The length of the transmission line to the next processor is short, the short transmission line enables skew correction of the clock, LSI, and transmission line. The outgoing line for a signal is unnecessary, and because only the next processor is driven, there are fewer limitations on the operating frequency. There is no limitation on the length of the connections, unlike the bus system and the number of connections is not limited electrically. Also, as for the bus system, the additional circuits are unnecessary, and less wiring is required than that for the bus system. Further, because all of the processors can see the content of the ring, the ring system is suitable for broadcast communication (snoop) for close-coupled inter-processor connection.
On the other hand, in the case of the ring connection system, the ring needs many pins in the order of two times that of the bus. The bus can transmit to all processors with one clock, but in the case of a ring, time delay for passage through processors is significant because of skew correction, clock synchronization, and control of transmission right, and in particular, the tightly-coupled inter-processor connection presents a problem.
Examples of application of a ring to inter-processor connections are described in, for example, IEEE Standard 1596H-1992, "Scaleable Coherent Interface (SCI)", 1992, or D. Cecchi, M. Dina, C. Preuss, "A IGB/S SCI Link in 0.8MBiCMOS," 1995 IEEE International Solid-State Circuits Conference, San Francisco, Calif., Digest of Technical Papers. Paper 20. 2, February 1995, pp. 326-327. SCI is the typical inter-processor connection described in the above-mentioned literature, however, it does not solve sufficiently the above-mentioned problem.
The structure of the interface of a ring is shown in FIG. 2 for the case in which the ring connection is used for establishing the inter-processor connection system.
In FIG. 2, a signal is received from a reception line 800 and stored in buffer 801. The flag and address are judged, then the signal is processed and transmitted to the receiving FIFO 807 or relay FIFO 806. A clock different from the reception clock, which operates in the area 802, is used for the modules of the processors, therefore buffers for absorbing the speed difference, namely receiving FIFO 807 and relay FIFO 806, are necessary. The receiving clock and the clock for the modules are different from each other in phase as a matter of course, therefore changing the clock is necessary between the buffer 801 and transmission processing 805. A signal is transmitted through the transfer latch 803 for transmission. Using a synchronous pattern periodically, signals are subjected to skew correction together before entering to the buffer 801. A packet for confirming the delivery is generated automatically and transmitted. Only one ring is used, and all the information is exchanged using the same packet form. A signal is subjected to cache coherence without using the broadcast function such as snoop. The cache coherence is ensured by using one-to-one packet communication. Failure detection, separation, and recovery are carried out through the ring, transfer pass of an ordinary packet.
As described herein above for the prior art, to use the processor bus (Here "bus" is used as a general term indicating means for connecting a processor to another processor or unit) properly, it is necessary to realize effectively the functions which are inherent in the processor bus by improving latency, throughput, and operability. Further, it is necessary to improve the time delay due to passage through processors in the ring connection, and to break the performance limit of the processor bus which has been based on the assumption that the processor bus is used for short distance connections.